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PIC18F6525_13 Datasheet, PDF (15/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D
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PIC18F6525/6621/8525/8621
TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
PIC18F6X2X PIC18F8X2X
Pin
Type
Buffer
Type
Description
PORTD is a bidirectional I/O port. These pins
have TTL input buffers when external
memory is enabled.
RD0/AD0/PSP0
RD0
AD0(3)
PSP0
58
72
I/O
ST
Digital I/O.
I/O
TTL
External memory address/data 0.
I/O
TTL
Parallel Slave Port data.
RD1/AD1/PSP1
RD1
AD1(3)
PSP1
55
69
I/O
ST
Digital I/O.
I/O
TTL
External memory address/data 1.
I/O
TTL
Parallel Slave Port data.
RD2/AD2/PSP2
RD2
AD2(3)
PSP2
54
68
I/O
ST
Digital I/O.
I/O
TTL
External memory address/data 2.
I/O
TTL
Parallel Slave Port data.
RD3/AD3/PSP3
RD3
AD3(3)
PSP3
53
67
I/O
ST
Digital I/O.
I/O
TTL
External memory address/data 3.
I/O
TTL
Parallel Slave Port data.
RD4/AD4/PSP4
RD4
AD4(3)
PSP4
52
66
I/O
ST
Digital I/O.
I/O
TTL
External memory address/data 4.
I/O
TTL
Parallel Slave Port data.
RD5/AD5/PSP5
RD5
AD5(3)
PSP5
51
65
I/O
ST
Digital I/O.
I/O
TTL
External memory address/data 5.
I/O
TTL
Parallel Slave Port data.
RD6/AD6/PSP6
RD6
AD6(3)
PSP6
50
64
I/O
ST
Digital I/O.
I/O
TTL
External memory address/data 6.
I/O
TTL
Parallel Slave Port data.
RD7/AD7/PSP7
RD7
AD7(3)
PSP7
49
63
I/O
ST
Digital I/O.
I/O
TTL
External memory address/data 7.
I/O
TTL
Parallel Slave Port data.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
O
= Output
P = Power
OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all
Program Memory modes except Microcontroller).
2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8525/8621 devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for
all PIC18F6525/6621 devices.
5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set.
8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in user or ICSP™ modes. See parameter D001 for details.
9: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
 2003-2013 Microchip Technology Inc.
DS39612C-page 15
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