PIC18F6525_13 Datasheet, PDF (392/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
Timer0 ............................................................................... 131
16-Bit Mode Timer Reads and Writes ....................... 133
Associated Registers ................................................ 133
Clock Source Edge Select (T0SE Bit)....................... 133
Clock Source Select (T0CS Bit) ................................ 133
Operation .................................................................. 133
Overflow Interrupt ..................................................... 133
Prescaler. See Prescaler, Timer0.
Timer1 ............................................................................... 135
16-Bit Read/Write Mode............................................ 137
Associated Registers ................................................ 139
Operation .................................................................. 136
Oscillator ........................................................... 135, 137
Overflow Interrupt ............................................. 135, 137
Special Event Trigger (ECCP) .......................... 137, 160
TMR1H Register ....................................................... 135
TMR1L Register ........................................................ 135
Use as a Real-Time Clock ........................................ 138
Timer2 ............................................................................... 141
Associated Registers ................................................ 142
MSSP Clock Shift.............................................. 141, 142
Operation .................................................................. 141
Postscaler. See Postscaler, Timer2.
PR2 Register............................................. 141, 154, 160
Prescaler. See Prescaler, Timer2.
TMR2 Register .......................................................... 141
TMR2 to PR2 Match Interrupt ........... 141, 142, 154, 160
Timer3 ............................................................................... 143
Associated Registers ................................................ 145
Operation .................................................................. 144
Oscillator ........................................................... 143, 145
Overflow Interrupt ............................................. 143, 145
Special Event Trigger (ECCP) .................................. 145
TMR3H Register ....................................................... 143
TMR3L Register ........................................................ 143
Timer4 ............................................................................... 147
Associated Registers ................................................ 148
MSSP Clock Shift...................................................... 148
Operation .................................................................. 147
Postscaler. See Postscaler, Timer4.
PR4 Register............................................................. 147
Prescaler. See Prescaler, Timer4.
TMR4 Register .......................................................... 147
TMR4 to PR4 Match Interrupt ........................... 147, 148
Timing Diagrams
A/D Conversion ......................................................... 355
Acknowledge Sequence ........................................... 206
Asynchronous Reception .......................................... 224
Asynchronous Transmission ..................................... 222
Asynchronous Transmission
(Back to Back)................................................... 222
Automatic Baud Rate Calculation ............................. 220
Auto-Wake-up Bit (WUE) During
Normal Operation.............................................. 225
Auto-Wake-up Bit (WUE) During Sleep .................... 225
Baud Rate Generator with Clock Arbitration ............. 200
BRG Reset Due to SDA Arbitration
During Start Condition....................................... 209
Brown-out Reset (BOR) ............................................ 341
Bus Collision During a Repeated Start
Condition (Case 1) ............................................ 210
Bus Collision During a Repeated Start
Condition (Case 2) ............................................ 210
Bus Collision During a Start
Condition (SCL = 0) .......................................... 209
Bus Collision During a Stop
Condition (Case 1)............................................ 211
Bus Collision During a Stop
Condition (Case 2)............................................ 211
Bus Collision During Start
Condition (SDA Only) ....................................... 208
Bus Collision for Transmit and
Acknowledge .................................................... 207
Capture/Compare/PWM
(All ECCP/CCP Modules) ................................. 343
CLKO and I/O ........................................................... 338
Clock Synchronization .............................................. 193
Clock/Instruction Cycle ............................................... 44
EUSART Synchronous
Receive (Master/Slave) .................................... 353
EUSART Synchronous
Transmission (Master/Slave)............................ 353
Example SPI Master Mode (CKE = 0) ...................... 345
Example SPI Master Mode (CKE = 1) ...................... 346
Example SPI Slave Mode (CKE = 0) ........................ 347
Example SPI Slave Mode (CKE = 1) ........................ 348
External Clock (All Modes Except PLL) .................... 337
External Memory Bus Timing for Sleep
(Microprocessor Mode)....................................... 77
External Memory Bus Timing for TBLRD
(Extended Microcontroller Mode) ....................... 76
External Memory Bus Timing for TBLRD
(Microprocessor Mode)....................................... 76
Full-Bridge PWM Output........................................... 165
Half-Bridge Output .................................................... 163
I²C Bus Data............................................................. 349
I²C Bus Start/Stop Bits ............................................. 349
I²C Master Mode
(7 or 10-Bit Transmission) ................................ 204
I²C Master Mode (7-Bit Reception)........................... 205
I²C Master Mode First Start Bit Timing ..................... 201
I²C Slave Mode (10-Bit Reception, SEN = 0) ........... 190
I²C Slave Mode (10-Bit Reception, SEN = 1) ........... 195
I²C Slave Mode (10-Bit Transmission) ..................... 191
I²C Slave Mode (7-Bit Reception, SEN = 0) ............. 188
I²C Slave Mode (7-Bit Reception, SEN = 1) ............. 194
I²C Slave Mode (7-Bit Transmission) ....................... 189
Low-Voltage Detect .................................................. 256
Master SSP I²C Bus Data......................................... 351
Master SSP I²C Bus Start/Stop Bits ......................... 351
Parallel Slave Port (PSP).......................................... 344
Parallel Slave Port (PSP) Read ................................ 130
Parallel Slave Port (PSP) Write ................................ 129
Program Memory Read ............................................ 339
Program Memory Write............................................. 340
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) ..................................... 170
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) ...................................... 170
PWM Direction Change ............................................ 167
PWM Direction Change at Near
100% Duty Cycle .............................................. 167
PWM Output ............................................................. 154
Repeated Start Condition ......................................... 202
Reset, Watchdog Timer (WDT),
Oscillator Start-up Timer (OST)
and Power-up Timer (PWRT) ........................... 341
Send Break Character Sequence ............................. 226
Slave Mode General Call Address Sequence
(7 or 10-Bit Address Mode) .............................. 196
DS39612C-page 392
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