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PIC18F6525_13 Datasheet, PDF (19/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D
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PIC18F6525/6621/8525/8621
TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
PIC18F6X2X PIC18F8X2X
Pin
Type
Buffer
Type
Description
PORTH is a bidirectional I/O port(6).
RH0/A16
RH0
A16
RH1/A17
RH1
A17
—
79
I/O
ST
Digital I/O.
O
TTL
External memory address 16.
—
80
I/O
ST
Digital I/O.
O
TTL
External memory address 17.
RH2/A18
RH2
A18
RH3/A19
RH3
A19
—
1
I/O
ST
Digital I/O.
O
TTL
External memory address 18.
—
2
I/O
ST
Digital I/O.
O
TTL
External memory address 19.
RH4/AN12/P3C
RH4
AN12
P3C(7)
RH5/AN13/P3B
RH5
AN13
P3B(7)
—
22
I/O
ST
Digital I/O.
I Analog
Analog input 12.
O
—
ECCP3 output P3C.
—
21
I/O
ST
Digital I/O.
I Analog
Analog input 13.
O
—
ECCP3 output P3B.
RH6/AN14/P1C
RH6
AN14
P1C(7)
RH7/AN15/P1B
RH7
AN15
P1B(7)
—
20
I/O
ST
Digital I/O.
I Analog
Analog input 14.
O
—
ECCP1 output P1C.
—
19
I/O
ST
Digital I/O.
I Analog
Analog input 15.
O
—
ECCP1 output P1B.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
O
= Output
P = Power
OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all
Program Memory modes except Microcontroller).
2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8525/8621 devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for
all PIC18F6525/6621 devices.
5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set.
8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in user or ICSP™ modes. See parameter D001 for details.
9: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
 2003-2013 Microchip Technology Inc.
DS39612C-page 19
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