PIC18F6525_13 Datasheet, PDF (358/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
FIGURE 27-24: A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
Q4
130
A/D CLK ¹³²
A/D DATA
9
8 7 ^{... ...} 2
1
0
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
NEW_DATA
TCY
DONE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 ns) which also disconnects the holding capacitor from the analog input.
TABLE 27-26: A/D CONVERSION REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min Max Units
Conditions
130 TAD
A/D Clock Period
PIC18F6525/6621/ 1.6
8525/8621
PIC18LF6X2X/8X2X 3.0
20⁽⁵⁾
20⁽⁵⁾
s TOSC based, VREF  3.0V
s TOSC based, VREF full range
PIC18F6525/6621/ 2.0
6.0
s A/D RC mode
8525/8621
PIC18LF6X2X/8X2X 3.0
9.0
s A/D RC mode
131 TCNV Conversion Time (not including acquisition 11
time) (Note 1)
12
TAD
132 TACQ Acquisition Time (Note 3)
15
—
s -40C  Temp  +125C
10
—
s 0C  Temp  +125C
135 TSWC Switching Time from Convert  Sample
— (Note 4)
136 TAMP Amplifier Settling Time (Note 2)
1
—
s This may be used if the
“new” input voltage has not
changed by more than 1 LSb
(i.e., 5 mV @ 5.12V) from the
last sampled voltage (as
stated on CHOLD).
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 20.0 “10-Bit Analog-to-Digital Converter (A/D) Module” for minimum conditions when input
voltage has changed more than 1 LSb.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is
50.
4: On the next Q4 cycle of the device clock.
5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
DS39612C-page 358
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