PIC18F6525_13 Datasheet, PDF (54/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
PORTJ⁽³⁾ Read PORTJ pins, Write PORTJ Data Latch
PORTH⁽³⁾ Read PORTH pins, Write PORTH Data Latch
xxxx xxxx
0000 xxxx
PORTG
—
—
RG5^{(4) Read PORTG pins, Write PORTG Data Latch}
--xx xxxx
PORTF
Read PORTF pins, Write PORTF Data Latch
x000 0000
PORTE
Read PORTE pins, Write PORTE Data Latch
xxxx xxxx
PORTD Read PORTD pins, Write PORTD Data Latch
xxxx xxxx
PORTC Read PORTC pins, Write PORTC Data Latch
xxxx xxxx
PORTB
PORTA
Read PORTB pins, Write PORTB Data Latch
—
RA6⁽¹⁾ Read PORTA pins, Write PORTA Data Latch⁽¹⁾
xxxx xxxx
-x0x 0000
SPBRGH1 Enhanced USART1 Baud Rate Generator Register High Byte
0000 0000
BAUDCON1
—
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN -1-0 0-00
SPBRGH2 Enhanced USART2 Baud Rate Generator Register High Byte
0000 0000
BAUDCON2
—
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN -1-0 0-00
ECCP1DEL P1RSEN P1DC6
P1DC5
P1DC4
P1DC3 P1DC2 P1DC1 P1DC0 0000 0000
TMR4
Timer4 Register
0000 0000
PR4
Timer4 Period Register
1111 1111
T4CON
—
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000
CCPR4H Capture/Compare/PWM Register 4 High Byte
xxxx xxxx
CCPR4L Capture/Compare/PWM Register 4 Low Byte
xxxx xxxx
CCP4CON
—
—
DC4B1
DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000
CCPR5H Capture/Compare/PWM Register 5 High Byte
xxxx xxxx
CCPR5L Capture/Compare/PWM Register 5 Low Byte
xxxx xxxx
CCP5CON
—
—
DC5B1
DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 --00 0000
SPBRG2 Enhanced USART2 Baud Rate Generator Register Low Byte
0000 0000
RCREG2 Enhanced USART2 Receive Register
0000 0000
TXREG2 Enhanced USART2 Transmit Register
0000 0000
TXSTA2
CSRC
TX9
TXEN
SYNC
SENDB BRGH
TRMT
TX9D 0000 0010
RCSTA2
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x
ECCP3AS ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000
ECCP3DEL P3RSEN P3DC6
P3DC5
P3DC4
P3DC3 P3DC2 P3DC1 P3DC0 0000 0000
ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000
ECCP2DEL P2RSEN P2DC6
P2DC5
P2DC4
P2DC3 P2DC2 P2DC1 P2DC0 0000 0000
Legend:
Note 1:
2:
3:
4:
5:
x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
RA6 and associated bits are configured as a port pin in RCIO and ECIO Oscillator modes only and read ‘0’ in all other
oscillator modes.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers are unused on PIC18F6525/6621 devices and read as ‘0’.
RG5 is available only if MCLR function is disabled in configuration.
Enabled only in Microcontroller mode for PIC18F8525/8621 devices.
35, 127
35, 124
36, 121
36, 119
36, 116
36, 113
36, 110
36, 108
36, 105
36, 217
36, 216
36, 217
36, 216
36, 168
36, 148
36, 148
36, 147
36, 153
36, 153
36, 149
36, 153
36, 153
36, 149
36, 217
36, 224
36, 222
36, 222
36, 222
36, 169
36, 168
36, 169
36, 168
DS39612C-page 54
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