PIC18F6525_13 Datasheet, PDF (297/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] INCFSZ f [,d [,a]
Operands:
0  f  255
d  [0,1]
a  [0,1]
Operation:
(f) + 1  dest;
skip if result = 0
Status Affected:
None
Encoding:
0011 11da ffff ffff
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then the
bank will be selected as per the BSR
value (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register ‘f’
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
Write to
destination
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
NZERO
ZERO
INCFSZ
:
:
CNT, 1, 0
Before Instruction
PC
=
After Instruction
CNT =
If CNT =
PC =
If CNT 
PC =
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
INFSNZ
Increment f, Skip if Not 0
Syntax:
[ label ] INFSNZ f [,d [,a]
Operands:
0  f  255
d  [0,1]
a  [0,1]
Operation:
(f) + 1  dest;
skip if result  0
Status Affected:
None
Encoding:
0100 10da ffff ffff
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then the
bank will be selected as per the BSR
value (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register ‘f’
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
Write to
destination
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
ZERO
NZERO
INFSNZ REG, 1, 0
Before Instruction
PC
=
After Instruction
REG =
If REG 
PC =
If REG =
PC =
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
 2003-2013 Microchip Technology Inc.
DS39612C-page 297