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PIC18F6525_13 Datasheet, PDF (309/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D | |||
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PIC18F6525/6621/8525/8621
RRNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Rotate Right f (No Carry)
[ label ] RRNCF f [,d [,a]
0 ï£ f ï£ 255
d ï [0,1]
a ï [0,1]
(f<n>) ï® dest<n â 1>;
(f<0>) ï® dest<7>
N, Z
0100 00da ffff ffff
The contents of register âfâ are rotated
one bit to the right. If âdâ is â0â, the result
is placed in W. If âdâ is â1â, the result is
placed back in register âfâ (default). If âaâ
is â0â, the Access Bank will be selected,
overriding the BSR value. If âaâ is â1â,
then the bank will be selected as per
the BSR value (default).
register f
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
1
1
Q2
Read
register âfâ
Q3
Process
Data
Q4
Write to
destination
Example 1:
RRNCF REG, 1, 0
Before Instruction
REG =
After Instruction
REG =
1101 0111
1110 1011
Example 2:
RRNCF REG, 0, 0
Before Instruction
W
=
REG =
After Instruction
W
=
REG =
?
1101 0111
1110 1011
1101 0111
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Set f
[ label ] SETF f [,a]
0 ï£ f ï£ 255
a ïï [0,1]
FFh ï® f
None
0110 100a ffff ffff
The contents of the specified register
are set to FFh. If âaâ is â0â, the Access
Bank will be selected, overriding the
BSR value. If âaâ is â1â, then the bank will
be selected as per the BSR value
(default).
1
1
Q2
Read
register âfâ
Q3
Process
Data
Q4
Write
register âfâ
Example:
SETF
Before Instruction
REG
=
After Instruction
REG
=
0x5A
0xFF
REG,1
ï£ 2003-2013 Microchip Technology Inc.
DS39612C-page 309
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