PIC18F6525_13 Datasheet, PDF (121/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
FIGURE 10-17: MCLR/VPP/RG5 PIN BLOCK DIAGRAM
MCLRE
Data Bus
RD TRISA
RD LATA
Schmitt
Trigger
Latch
QD
EN
MCLR/VPP/RG5
RD PORTA
High-Voltage Detect
Internal MCLR
Filter
HV
Low-Level
MCLR Detect
TABLE 10-13: PORTG FUNCTIONS
Name
Bit# Buffer Type
Function
RG0/ECCP3/P3A
bit 0
ST
RG1/TX2/CK2
bit 1
ST
RG2/RX2/DT2
bit 2
ST
RG3/CCP4/P3D
bit 3
ST
RG4/CCP5/P1D
bit 4
ST
MCLR/VPP/RG5
bit 5
ST
Legend: ST = Schmitt Trigger input
Input/output port pin, Enhanced Capture 3 input/Compare 3 output/
PWM 3 output or Enhanced PWM 3 output P3A.
Input/output port pin, addressable USART2 asynchronous transmit or
addressable USART2 synchronous clock.
Input/output port pin, addressable USART2 asynchronous receive or
addressable USART2 synchronous data.
Input/output port pin, Capture 4 input/Compare 4 output/PWM 4 output
or Enhanced PWM 3 output P3D.
Input/output port pin, Capture 5 input/Compare 5 output/PWM 5 output
or Enhanced PWM 1 output P1D.
Master Clear input or programming voltage input (if MCLR is enabled).
Input only port pin or programming voltage input (if MCLR is
disabled).
TABLE 10-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PORTG
—
— RG5⁽¹⁾ Read PORTG pins/Write PORTG Data Latch
LATG
—
—
— LATG Data Output Register
TRISG
—
—
— Data Direction Control Register for PORTG
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’
Note 1: RG5 is available as an input only when MCLR is disabled.
Value on
POR, BOR
Value on
all other
Resets
--xx xxxx --uu uuuu
---x xxxx ---u uuuu
---1 1111 ---1 1111
 2003-2013 Microchip Technology Inc.
DS39612C-page 121