PIC18F6525_13 Datasheet, PDF (227/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
19.3 EUSART Synchronous
Master Mode
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTAx<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit
SYNC (TXSTAx<4>). In addition, enable bit SPEN
(RCSTAx<7>) is set in order to configure the TXx and
RXx pins to CKx (clock) and DTx (data) lines,
respectively.
The Master mode indicates that the processor trans-
mits the master clock on the CKx line. Clock polarity is
selected with the SCKP bit (BAUDCONx<4>); setting
SCKP sets the Idle state on CKx as high, while clearing
the bit sets the Idle state as low. This option is provided
to support Microwire devices with this module.
19.3.1 EUSART SYNCHRONOUS MASTER
TRANSMISSION
The EUSART transmitter block diagram is shown in
Figure 19-2. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREGx. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREGx (if available).
Once the TXREGx register transfers the data to the
TSR register (occurs in one TCYCLE), the TXREGx is
empty and interrupt bit TXxIF is set. The interrupt can
be enabled/disabled by setting/clearing enable bit
TXxIE. Flag bit TXxIF will be set regardless of the state
of enable bit TXxIE and cannot be cleared in software.
It will reset only when new data is loaded into the
TXREGx register.
While flag bit TXxIF indicates the status of the TXREGx
register, another bit, TRMT (TXSTAx<1>), shows the
status of the TSR register. TRMT is a read-only bit which
is set when the TSR is empty. No interrupt logic is tied to
this bit so the user has to poll this bit in order to deter-
mine if the TSR register is empty. The TSR is not
mapped in data memory so it is not available to the user.
To set up a Synchronous Master Transmission:
1. Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRG16 bit, as required, to achieve the desired
baud rate.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit TXxIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREGx register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 19-10: SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1
pin
RC6/TX1/CK1 pin
(SCKP = 0)
RC6/TX1/CK1 pin
(SCKP = 1)
bit 0
bit 1
bit 2
Word 1
Write to
TXREG1 Reg
TX1IF bit
(Interrupt Flag)
Write Word 1
Write Word 2
TRMT bit
TXEN bit
‘1’
Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 7
bit 0
bit 1
bit 7
Word 2
‘1’
Note: Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words.
 2003-2013 Microchip Technology Inc.
DS39612C-page 227