PIC18F6525_13 Datasheet, PDF(32/400 Page) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

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PIC18F6525_13 Datasheet, PDF (32/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

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PIC18F6525/6621/8525/8621

TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS

Register

Applicable Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

TOSU

TOSH

TOSL

STKPTR

Feature1

Feature1

Feature1

Feature1

Feature2

Feature2

Feature2

Feature2

---0 0000

0000 0000

0000 0000

00-0 0000

---0 0000

0000 0000

0000 0000

uu-0 0000

---0 uuuu(3)

uuuu uuuu(3)

uuuu uuuu(3)

uu-u uuuu(3)

PCLATU

Feature1 Feature2

---0 0000

---0 0000

---u uuuu

PCLATH

PCL

Feature1

Feature1

Feature2

Feature2

0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu

PC + 2(2)

TBLPTRU

Feature1 Feature2

--00 0000

--00 0000

--uu uuuu

TBLPTRH

Feature1 Feature2

0000 0000

0000 0000

uuuu uuuu

TBLPTRL

Feature1 Feature2

0000 0000

0000 0000

uuuu uuuu

TABLAT

Feature1 Feature2

0000 0000

0000 0000

uuuu uuuu

PRODH

Feature1 Feature2

xxxx xxxx

uuuu uuuu

uuuu uuuu

PRODL

INTCON

INTCON2

INTCON3

Feature1

Feature1

Feature1

Feature1

Feature2

Feature2

Feature2

Feature2

xxxx xxxx

0000 000x

1111 1111

1100 0000

uuuu uuuu

0000 000u

1111 1111

1100 0000

uuuu uuuu

uuuu uuuu(1)

uuuu uuuu(1)

uuuu uuuu(1)

INDF0

Feature1 Feature2

N/A

N/A

N/A

POSTINC0

Feature1 Feature2

N/A

N/A

N/A

POSTDEC0

Feature1

Feature2

N/A

N/A

N/A

PREINC0

Feature1 Feature2

N/A

N/A

N/A

PLUSW0

Feature1 Feature2

N/A

N/A

N/A

FSR0H

Feature1 Feature2

---- 0000

---- 0000

---- uuuu

FSR0L

Feature1 Feature2

xxxx xxxx

uuuu uuuu

uuuu uuuu

WREG

Feature1 Feature2

xxxx xxxx

uuuu uuuu

uuuu uuuu

INDF1

Feature1 Feature2

N/A

N/A

N/A

POSTINC1

Feature1 Feature2

N/A

N/A

N/A

POSTDEC1

Feature1

Feature2

N/A

N/A

N/A

PREINC1

Feature1 Feature2

N/A

N/A

N/A

PLUSW1

Feature1 Feature2

N/A

N/A

N/A

FSR1H

Feature1 Feature2

---- 0000

---- 0000

---- uuuu

Legend:

Note 1:

2:

3:

4:

5:

6:

7:

8:

9:

u = unchanged, x = unknown, - = unimplemented bit, read as â0â, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

See Table 3-2 for Reset value for specific condition.

Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read â0â.

Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read â0â.

If MCLR function is disabled, PORTG<5> is a read-only bit.

Enabled only in Microcontroller mode for PIC18F8525/8621 devices.

The MEMCON register is unimplemented and reads all â0âs when the device is in Microcontroller mode.

DS39612C-page 32

ï£ 2003-2013 Microchip Technology Inc.

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