PIC18F6525_13 Datasheet, PDF (393/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
Slave Synchronization .............................................. 179
Slow Rise Time (MCLR Tied to VDD
via 1 kResistor)................................................ 38
SPI Mode (Master Mode) .......................................... 178
SPI Mode (Slave Mode with CKE = 0) ...................... 180
SPI Mode (Slave Mode with CKE = 1) ...................... 180
Stop Condition Receive or Transmit Mode ............... 206
Synchronous Reception
(Master Mode, SREN)....................................... 229
Synchronous Transmission....................................... 227
Synchronous Transmission (Through TXEN) ........... 228
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD via 1 k Resistor) ............... 38
Time-out Sequence on Power-up (MCLR
Not Tied to VDD): Case 1 .................................... 37
Time-out Sequence on Power-up (MCLR
Not Tied to VDD): Case 2 .................................... 37
Time-out Sequence on Power-up (MCLR
Tied to VDD via 1 k Resistor) ............................ 37
Timer0 and Timer1 External Clock ........................... 342
Timing for Transition Between Timer1 and
OSC1 (EC with PLL Active, SCS1 = 1)............... 27
Timing for Transition Between Timer1 and
OSC1 (HS with PLL Active, SCS1 = 1)............... 27
Transition Between Timer1 and
OSC1 (HS, XT, LP)............................................. 26
Transition Between Timer1 and
OSC1 (RC, EC)................................................... 28
Transition from OSC1 to Timer1 Oscillator ................. 26
Wake-up from Sleep via Interrupt ............................. 270
Timing Specifications ........................................................ 337
A/D Conversion Requirements ................................. 355
Capture/Compare/PWM Requirements .................... 343
CLKO and I/O Requirements .................................... 338
EUSART Synchronous Receive
Requirements.................................................... 353
EUSART Synchronous Transmission
Requirements.................................................... 353
Example SPI Mode Requirements
(Master Mode, CKE = 0) ................................... 345
Example SPI Mode Requirements
(Master Mode, CKE = 1) ................................... 346
Example SPI Mode Requirements
(Slave Mode, CKE = 0) ..................................... 347
Example SPI Slave Mode
Requirements (CKE = 1)................................... 348
External Clock Requirements ................................... 337
I²C Bus Data Requirements (Slave Mode) ............... 350
I²C Bus Start/Stop Bits Requirements
(Slave Mode) .................................................... 349
Master SSP I²C Bus Data Requirements ................. 352
Master SSP I²C Bus Start/Stop Bits
Requirements ................................................... 351
Parallel Slave Port Requirements............................. 344
PLL Clock ................................................................. 338
Program Memory Read Requirements ..................... 339
Program Memory Write Requirements ..................... 340
Reset, Watchdog Timer, Oscillator
Start-up Timer, Power-up Timer
and Brown-out Reset Requirements ................ 341
Timer0 and Timer1 External
Clock Requirements ......................................... 342
TRISE Register
PSPMODE Bit................................................... 111, 128
TSTFSZ ............................................................................ 315
Two-Word Instructions
Example Cases........................................................... 46
TXSTAx Register
BRGH Bit .................................................................. 217
V
Voltage Reference Specifications..................................... 332
W
Wake-up from Sleep ................................................. 259, 269
Using Interrupts ........................................................ 269
Watchdog Timer (WDT)............................................ 259, 267
Associated Registers ................................................ 268
Control Register........................................................ 267
Postscaler ................................................................. 268
Programming Considerations ................................... 267
RC Oscillator............................................................. 267
Time-out Period ........................................................ 267
WCOL ....................................................... 201, 202, 203, 206
WCOL Status Flag.................................... 201, 202, 203, 206
WWW, On-Line Support ....................................................... 5
X
XORLW............................................................................. 315
XORWF ............................................................................ 316
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DS39612C-page 393