PIC18F6525_13 Datasheet, PDF (311/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
SUBLW
Subtract W from Literal
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
[ label ] SUBLW k
0 k 255
k – (W) W
N, OV, C, DC, Z
0000 1000 kkkk kkkk
W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
1
1
Q2
Read
literal ‘k’
Q3
Process
Data
Q4
Write to W
Example 1:
SUBLW 0x02
Before Instruction
W
=1
C
=?
After Instruction
W
=1
C
=1
Z
=0
N
=0
; result is positive
Example 2:
SUBLW 0x02
Before Instruction
W
=2
C
=?
After Instruction
W
=0
C
= 1 ; result is zero
Z
=1
N
=0
Example 3:
SUBLW 0x02
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
3
?
FF ; (2’s complement)
0 ; result is negative
0
1
SUBWF
Subtract W from f
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
[ label ] SUBWF f [,d [,a]
0 f 255
d  [0,1]
a  [0,1]
(f) – (W) dest
N, OV, C, DC, Z
0101 11da ffff ffff
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ is ‘1’, then the bank will be
selected as per the BSR value
(default).
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Example 1:
SUBWF REG, 1, 0
Before Instruction
REG = 3
W
=2
C
=?
After Instruction
REG = 1
W
=2
C
=1
Z
=0
N
=0
; result is positive
Example 2:
SUBWF REG, 0, 0
Before Instruction
REG = 2
W
=2
C
=?
After Instruction
REG = 2
W
=0
C
=1
Z
=1
N
=0
; result is zero
Example 3:
SUBWF REG, 1, 0
Before Instruction
REG =
W
=
C
=
After Instruction
REG =
W
=
C
=
Z
=
N
=
1
2
?
FFh ;(2’s complement)
2
0 ; result is negative
0
1
 2003-2013 Microchip Technology Inc.
DS39612C-page 311