PIC18F6525_13 Datasheet, PDF (18/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
PIC18F6X2X PIC18F8X2X
Pin
Type
Buffer
Type
Description
PORTG is a bidirectional I/O port.
RG0/ECCP3/P3A
3
RG0
ECCP3
P3A
5
I/O
ST
Digital I/O.
I/O
ST
Enhanced Capture 3 input, Compare 3
output, PWM 3 output.
O
—
ECCP3 output P3A.
RG1/TX2/CK2
RG1
TX2
CK2
4
6
I/O
ST
Digital I/O.
O
—
USART2 asynchronous transmit.
I/O
ST
USART2 synchronous clock
(see RX2/DT2).
RG2/RX2/DT2
RG2
RX2
DT2
5
7
I/O
ST
Digital I/O.
I
ST
USART2 asynchronous receive.
I/O
ST
USART2 synchronous data
(see TX2/CK2).
RG3/CCP4/P3D
6
8
RG3
I/O
ST
Digital I/O.
CCP4
I/O
ST
Capture 4 input, Compare 4 output,
PWM 4 output.
P3D
O
—
ECCP3 output P3D.
RG4/CCP5/P1D
RG4
CCP5
P1D
8
10
I/O
ST
Digital I/O.
I/O
ST
Capture 5 input, Compare 5 output,
PWM 5 output.
O
—
ECCP1 output P1D.
RG5
7
9
—
— See MCLR/VPP/RG5 pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
O
= Output
P = Power
OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all
Program Memory modes except Microcontroller).
2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8525/8621 devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for
all PIC18F6525/6621 devices.
5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set.
8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in user or ICSP™ modes. See parameter D001 for details.
9: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
DS39612C-page 18
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