PIC18F6525_13 Datasheet, PDF (35/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
IPR3
Feature1 Feature2
--11 1111
--11 1111
--uu uuuu
PIR3
Feature1 Feature2
--00 0000
--00 0000
--uu uuuu
PIE3
Feature1 Feature2
--00 0000
--00 0000
--uu uuuu
IPR2
PIR2
Feature1
Feature1
Feature2
Feature2
-1-1 1111
-0-0 0000
-1-1 1111
-0-0 0000
-u-u uuuu
-u-u uuuu⁽¹⁾
PIE2
Feature1 Feature2
-0-0 0000
-0-0 0000
-u-u uuuu
IPR1
PIR1
Feature1
Feature1
Feature2
Feature2
1111 1111
0000 0000
1111 1111
0000 0000
uuuu uuuu
uuuu uuuu⁽¹⁾
PIE1
MEMCON⁽⁹⁾
Feature1
Feature1
Feature2
Feature2
0000 0000
0-00 --00
0000 0000
0-00 --00
uuuu uuuu
u-uu --uu
TRISJ
Feature1 Feature2
1111 1111
1111 1111
uuuu uuuu
TRISH
Feature1 Feature2
1111 1111
1111 1111
uuuu uuuu
TRISG
Feature1 Feature2
---1 1111
---1 1111
---u uuuu
TRISF
Feature1 Feature2
1111 1111
1111 1111
uuuu uuuu
TRISE
Feature1 Feature2
1111 1111
1111 1111
uuuu uuuu
TRISD
Feature1 Feature2
1111 1111
1111 1111
uuuu uuuu
TRISC
Feature1 Feature2
1111 1111
1111 1111
uuuu uuuu
TRISB
TRISA^(5,6)
Feature1
Feature1
Feature2
Feature2
1111 1111
-111 1111⁽⁵⁾
1111 1111
-111 1111⁽⁵⁾
uuuu uuuu
-uuu uuuu⁽⁵⁾
LATJ
Feature1 Feature2
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATH
Feature1 Feature2
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATG
Feature1 Feature2
---x xxxx
---u uuuu
---u uuuu
LATF
Feature1 Feature2
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATE
Feature1 Feature2
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATD
Feature1 Feature2
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATC
Feature1 Feature2
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATB
LATA^(5,6)
Feature1
Feature1
Feature2
Feature2
xxxx xxxx
-xxx xxxx⁽⁵⁾
uuuu uuuu
-uuu uuuu⁽⁵⁾
uuuu uuuu
-uuu uuuu⁽⁵⁾
PORTJ
Feature1 Feature2
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTH
Feature1 Feature2
0000 xxxx
0000 uuuu
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1:
2:
3:
4:
5:
6:
7:
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
See Table 3-2 for Reset value for specific condition.
Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
If MCLR function is disabled, PORTG<5> is a read-only bit.
8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.
9: The MEMCON register is unimplemented and reads all ‘0’s when the device is in Microcontroller mode.
 2003-2013 Microchip Technology Inc.
DS39612C-page 35