PIC18F6525_13 Datasheet, PDF (27/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
If the main oscillator is configured for HS mode with
PLL active, an oscillator start-up time (TOST) plus an
additional PLL time-out (TPLL) will occur. The PLL time-
out is typically 2 ms and allows the PLL to lock to the
main oscillator frequency. A timing diagram, indicating
the transition from the Timer1 oscillator to the main
oscillator for HS+PLL mode, is shown in Figure 2-10.
FIGURE 2-10:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1
(HS WITH PLL ACTIVE, SCS1 = 1)
Q4
Q1
T1OSI
OSC1
PLL Clock
Input
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter PC
TOST
TPLL
Note: TOST = 1024 TOSC (drawing not to scale).
TT1P
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TOSC
TSCS
1 23 4 56 78
PC + 2
PC + 4
If the main oscillator is configured for EC mode with PLL
active, only PLL time-out (TPLL) will occur. The PLL time-
out is typically 2 ms and allows the PLL to lock to the
main oscillator frequency. A timing diagram, indicating
the transition from the Timer1 oscillator to the main
oscillator for EC with PLL active, is shown in Figure 2-11.
FIGURE 2-11:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1
(EC WITH PLL ACTIVE, SCS1 = 1)
Q4
Q1
T1OSI
OSC1
PLL Clock
Input
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter PC
TPLL
TT1P
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TOSC
TSCS
1 2 34 56 78
PC + 2
PC + 4
 2003-2013 Microchip Technology Inc.
DS39612C-page 27