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HD6433937 Datasheet, PDF (97/521 Pages) Hitachi Semiconductor – Hardware Manual
Section 4 Clock Pulse Generators
4.1 Overview
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a
system clock pulse generator and a subclock pulse generator. The system clock pulse generator
consists of a system clock oscillator and system clock dividers. The subclock pulse generator
consists of a subclock oscillator circuit and a subclock divider.
4.1.1 Block Diagram
Figure 4-1 shows a block diagram of the clock pulse generators.
OSC1
OSC2
DX1
DX2
System clock
oscillator
øOSC
(f OSC)
System clock pulse generator
System clock
divider (1/2)
øOSC/2
System
clock
divider
øOSC/128
øOSC/64
øOSC/32
øOSC/16
Subclock
oscillator
Subclock
oscillator
(1/2)
øW
Subclock
divider
(fW) (1/2, 1/4, 1/8)
øW /2
øW /4
øW /8
ø
Prescaler S
(13 bits)
øSUB
Subclock pulse generator
Prescaler W
(5 bits)
Figure 4-1 Block Diagram of Clock Pulse Generators
ø/2
to
ø/8192
øDEC
øW
øW /2
øW /4
øW /8
to
øW /128
4.1.2 System Clock and Subclock
The basic clock signals that drive the CPU and on-chip peripheral modules are ø and øSUB. Five of
the clock signals have names: ø is the system clock, øSUB is the subclock, øOSC is the oscillator
clock, øw is the watch clock, and øDEC is the decoder clock.
The clock signals available for use by peripheral modules are ø/2, ø/4, ø/8, ø/16, ø/32, ø/64, ø/128,
ø/256, ø/512, ø/1024, ø/2048, ø/4096, ø/8192, øW, øW/2, øW/4, øW/8, øW/16, øW/32, øW/64, øW/128,
and øDEC. The clock requirements differ from one module to another.
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