HD6433937 Datasheet, PDF (233/521 Pages) Hitachi Semiconductor – Hardware Manual

5. Clock stop register 1 (CKSTPR1)
Bit
7
6
5
4
3
2
1
0
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer G is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 3: Timer G module standby mode control (TGCKSTP)
Bit 3 controls setting and clearing of module standby mode for timer G.
TGCKSTP
0
1
Description
Timer G is set to module standby mode
Timer G module standby mode is cleared
(initial value)
9.5.3 Noise Canceler
The noise canceler consists of a digital low-pass filter that eliminates high-frequency component
noise from the pulses input from the input capture input pin. The noise canceler is set by NCS* in
PMR3.
Figure 9-9 shows a block diagram of the noise canceler.
Sampling
clock
Input capture
input signal
C
D
Q
Latch
C
D
Q
Latch
C
D
Q
Latch
C
D
Q
Latch
C
D
Q
Latch
Match
detector
Noise
canceler
output
∆t
Sampling clock
∆t: Set by CKS1 and CKS0
Figure 9-9 Noise Canceler Block Diagram
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