HD6433937 Datasheet, PDF (236/521 Pages) Hitachi Semiconductor – Hardware Manual

2. Increment timing
TCG is incremented by internal clock input. Bits CKS1 and CKS0 in TMG select one of four
internal clock sources (ø/64, ø/32, ø/2, or øw/4) created by dividing the system clock (ø) or watch
clock (øw).
3. Input capture input timing
a. Without noise cancellation function
For input capture input, dedicated input capture functions are provided for rising and
falling edges.
Figure 9-11 shows the timing for rising/falling edge input capture input.
Input capture
input signal
Input capture
signal F
Input capture
signal R
Figure 9-11 Input Capture Input Timing (without Noise Cancellation Function)
b. With noise cancellation function
When noise cancellation is performed on the input capture input, the passage of the input
capture signal through the noise canceler results in a delay of five sampling clock cycles
from the input capture input signal edge.
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