HD6433937 Datasheet, PDF (259/521 Pages) Hitachi Semiconductor – Hardware Manual

Bit 7: Reserved bit
Bits 7 is reserved; it is always read as 1 and cannot be modified.
Bit 6: Extension data bit (SOL)
The SOL bit changes the output level of the SO₁. When read, SOL returns the output level of the
SO₁. After transfer is completed, SO₁ output retains the value of the last bit of the transmit data,
and therefore the SO₁ output level can be changed by manipulating this bit before or after
transmission. However, the SOL bit setting becomes invalid when the next transmission starts*.
Therefore, when changing the SO₁ output level after transmission, a write operation must be
performed on the SOL bit each time transmission is completed. Writing to this register during data
transfer will cause incorrect operation, so this register should not be manipulated during
transmission.
Note: * The SOL bit setting is also invalid in SSB mode.
Bit 6
SOL
0
1
Description
Read
Write
Read
Write
SO₁ output level is low
Changes SO₁ output to low level
SO₁ output level is high
Changes SO₁ output to high level
(initial value)
Bit 5: Overrun error flag (ORER)
Bit 5 indicates that an overrun error has occurred when using an external clock. If extra pulses are
superimposed on the regular serial clock due to extraneous noise, etc., the transfer data cannot be
guaranteed. If the clock is input after transfer is completed, this will be interpreted as an overrun
state and this bit will be set to 1.
Bit 5
ORER
0
1
Description
Clearing conditions:
After reading ORER = 1, cleared by writing 0 to ORER
(initial value)
Setting conditions:
When an external clock is used and the clock is input after transfer is completed
Bits 4 to 2: Reserved bits
Bits 4 to 2 are reserved; they are always read as 1 and cannot be modified.
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