HD6433937 Datasheet, PDF (77/521 Pages) Hitachi Semiconductor – Hardware Manual

2. Interrupt enable register 1 (IENR1)
Bit
7
6
5
Initial value
Read/Write
IENTA
0
R/W
IENS1
0
R/W
IENWP
0
R/W
4
IEN4
0
R/W
3
IEN3
0
R/W
2
IEN2
0
R/W
1
IEN1
0
R/W
0
IEN0
0
R/W
IENR1 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7: Timer A interrupt enable (IENTA)
Bit 7 enables or disables timer A overflow interrupt requests.
Bit 7
IENTA
0
1
Description
Disables timer A interrupt requests
Enables timer A interrupt requests
(initial value)
Bit 6: SCI1 interrupt enable (IENS1)
Bit 6 enables or disables SCI1 transfer complete interrupt requests.
Bit 6
IENS1
Description
0
Disables SCI1 interrupt requests
(initial value)
1
Enables SCI1 interrupt requests
Note: SCI1 is an internal function that performs interfacing to the FLEX™ decoder incorporated in
the chip.
Bit 5: Wakeup interrupt enable (IENWP)
Bit 5 enables or disables WKP₇ to WKP₀ interrupt requests.
Bit 5
IENWP
0
1
Description
Disables WKP₇ to WKP₀ interrupt requests
Enables WKP₇ to WKP₀ interrupt requests
(initial value)
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