HD6433937 Datasheet, PDF (401/521 Pages) Hitachi Semiconductor – Hardware Manual

12.6.2 Start-up Timing
The following diagram and table describe the timing specifications of the FLEX decoder when
power is applied.
VDD
Oscillator
t_START
RESET
READY
t_RESET
t_RHRL
Figure 12-14 Start-up Timing
Table 12-35 Start-up Timing (V_DD = 1.8 V to 3.6 V, T_A = -20ºC to 75ºC)
Characteristic
Conditions Symbol
Min*¹
Max *¹
Unit
Oscillator Start-up Time
RESET Hold Time
RESET High to READY
Low
t _START
t _RESET
t _RHRL
5
sec
200
ns
76,800
76,800
T*²
Notes: 1. The specifications given in this data sheet indicate the minimum performance level of all
manufacturers of the FLEX decoder. Individual manufacturers may have better
performance than indicated.
2. T is one period of the ø_DEC clock source. Note that from power-up, the oscillator start-up
time can impact the availability and period of clock strobes. This can affect the actual
RESET high to READY low timing.
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