HD6433937 Datasheet, PDF (80/521 Pages) Hitachi Semiconductor – Hardware Manual

4. Interrupt request register 1 (IRR1)
Bit
7
6
5
IRRTA IRRS1 —
Initial value
0
0
1
Read/Write R/(W)* R/(W)* —
4
IRRI4
0
R/(W)*
3
IRRI3
0
R/(W)*
2
IRRI2
0
R/(W)*
1
IRRI1
0
R/(W)*
0
IRRI0
0
R/(W)*
Note: * Only a write of 0 for flag clearing is possible
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A,
SCI1, or IRQ₄ to IRQ₀ interrupt is requested. The flags are not cleared automatically when an
interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit 7: Timer A interrupt request flag (IRRTA)
Bit 7
IRRTA
0
1
Description
Clearing conditions:
When IRRTA = 1, it is cleared by writing 0
Setting conditions:
When the timer A counter value overflows from H'FF to H'00
(initial value)
Bit 6: SCI1 interrupt request flag (IRRS1)
Bit 6
IRRS1
Description
0
Clearing conditions:
When IRRS1 = 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When SCI1 completes transfer
Note: SCI1 is an internal function that performs interfacing to the FLEX™ decoder incorporated in
the chip.
Bit 5: Reserved bit
Bit 5 is reserved; it is always read as 1 and cannot be modified.
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