HD6433937 Datasheet, PDF (285/521 Pages) Hitachi Semiconductor – Hardware Manual

Table 10-7 Relation between n and Clock
SMR Setting
n
Clock
CKS1
CKS0
0
ø
0
0
0
ø_W/2*¹/ø_W*²
0
1
2
ø/16
1
0
3
ø/64
1
1
Notes: 1. ø_W/2 clock is selected in active (medium- and high-speed) or sleep (medium- and high-
speed) mode.
2. ø_W clock is selected in subactive or subsleep mode. SCI3 can be used only when the
ø_W/2 is selected as the CPU clock in subactive or subsleep mode.
Table 10-8 shows the maximum bit rate for each frequency. The values shown are for active
(high-speed) mode.
Table 10-8 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Setting
OSC (MHz)
Maximum Bit Rate (bit/s)
n
N
0.0384*
600
0
0
2
31250
0
0
2.4576
38400
0
0
4
62500
0
0
10
156250
0
0
16
250000
0
0
Note: * When SMR is set up to CKS1 = 0, CKS0 = 1.
Table 10-9 shows examples of BRR settings in synchronous mode. The values shown are for
active (high-speed) mode.
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