HD6433937 Datasheet, PDF (400/521 Pages) Hitachi Semiconductor – Hardware Manual

Table 12-34 SPI Timing (VDD = 1.8 V to 3.6 V, TA = -20ºC to 75ºC)
Characteristic
Conditions
Symbol Min*¹ Max*¹ Unit
Operating Frequency
f _OP
dc 1
MHz
Cycle Time
t_CYC
1000
ns
Select Lead Time
t _LEAD1
200
ns
De-select Lag Time
t _LAG1
200
ns
Select-to-Ready Time previous packet did not program an
t _RDY
address word*² C_L =50pf
80 µs
Select-to-Ready Time previous packet programmed an address t_RDY
word*² C_L =50pf
420 µs
Re-select Time
previous packet was a checksum/special t_RS
30
µs
packet*³ C_L =50pf
Ready High Time
t _RH
50
µs
Ready Lead Time
t _LEAD2
200
ns
Not Ready Lag Time C_L =50pf
t _LAG2
200 ns
MOSI Data Setup Time
t _SU
200
ns
MOSI Data Hold Time
t _HI
200
ns
MISO Access Time
C_L =50pf
t _AC
0
200 ns
MISO Disable Time
t _DIS
300 ns
MISO Data Valid Time C_L =50pf
t_V
200 ns
MISO Data Hold Time
t _HO
0
ns
SS High Time
t _SSH
200
ns
SCK High Time
t _SCKH
300
ns
SCK Low Time
t _SCKL
300
ns
SCK Rise Time
20% to 70% V_DD
t_R
1
µs
SCK Fall Time
20% to 70% V_DD
t_F
1
µs
Notes: 1. The specifications given in this data sheet indicate the minimum performance level of
all FLEX decoders regardless of manufacturer. Individual manufacturers may have
better performance than indicated.
2. When the host re-programs an address word with a Host-to-Decoder packet ID > 127
(decimal), there may be an added delay before the FLEX decoder is ready for another
packet.
3. When the host sends a checksum packet (ID is 00) or a special packet (ID is 1C
through 1F hex) the t_RS specification applies, otherwise the timing specifications for t_LAG1
and t_SSH govern the re-select timing.
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