HD6433937 Datasheet, PDF (139/521 Pages) Hitachi Semiconductor – Hardware Manual

Figure 6-5 shows a PROM write/verify timing diagram.
Address
Data
VPP
VPP
VCC
Write
tAS
Input data
tDS
tDH
tVPS
Verify
tAH
Output data
tDF
VCC
VCC+1
VCC
tVCS
CE
PGM
OE
tCES
tPW
tOPW*
tOES
tOE
Note: * topw is defined by the value shown in figure 6.4, High-Speed, High-Reliability Programming Flowchart.
Figure 6-5 PROM Write/Verify Timing
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