HD6433937 Datasheet, PDF (455/521 Pages) Hitachi Semiconductor – Hardware Manual

RDR32—Receive data register 32
H'AD
SCI32
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
RDR327 RDR326 RDR325 RDR324 RDR323 RDR322 RDR321 RDR320
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Serial receive data
TMA—Timer mode register A
H'B0
Timer A
Bit
7
6
5
4
3
2
1
0
TMA7 TMA6 TMA5
—
TMA3 TMA2 TMA1 TMA0
Initial value
0
0
0
1
0
0
0
0
Read/Write
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
Clock output select* Internal clock select
0 0 0 ø/32
Prescaler and Divider Ratio
0 0 1 ø/16
TMA3 TMA2 TMA1 TMA0 or Overflow Period
0 1 0 ø/8
0
0
0
0 PSS
ø/8192
0 1 1 ø/4
0
0
0
1 PSS
ø/4096
1 0 0 ø_W/32
0
0
1
0 PSS
1 0 1 ø_W/16
0
0
1
1 PSS
1 1 0 ø_W/8
0
1
0
0 PSS
1 1 1 ø_W/4
0
1
0
1 PSS
Note: * Values when
0
1
1
0 PSS
bit CWOS = 0 ⁰
1
1
1 PSS
ø/2048
ø/512
ø/256
ø/128
ø/32
ø/8
in CWOSR.
1
0
0
0 PSW
When bit
1
0
0
1 PSW
CWOS = 1,
øw is output
1
0
1
0 PSW
ø_W/32768
ø_W/16384
ø_W/8192
regardless of 1
0
1
1 PSW
ø_W/1024
the value of
1
1
0
0 PSW and TCA are reset
bits TMA7 to
TMA5.
1
1
0
1
1
1
1
0
1
1
1
1
Function
Interval
timer
Time
base
(overflow
period)
443