HD6433937 Datasheet, PDF (185/521 Pages) Hitachi Semiconductor – Hardware Manual

8.11 Port A
8.11.1 Overview
Port A is a 4-bit I/O port, configured as shown in figure 8-10.
PA₃
Port A
PA₂
PA₁
PA₀
Figure 8-10 Port A Pin Configuration
8.11.2 Register Configuration and Description
Table 8-29 shows the port A register configuration.
Table 8-29 Port A Registers
Name
Port data register A
Port control register A
Abbrev. R/W
PDRA
R/W
PCRA
W
Initial Value
H'F0
H'F0
Address
H'FFDD
H'FFED
1. Port data register A (PDRA)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
PA ₃
PA ₂
PA ₁
PA ₀
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
PDRA is an 8-bit register that stores data for port A pins PA₃ to PA₀. If port A is read while
PCRA bits are set to 1, the values stored in PDRA are read, regardless of the actual pin states. If
port A is read while PCRA bits are cleared to 0, the pin states are read.
Upon reset, PDRA is initialized to H'F0.
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