HD6433937 Datasheet, PDF (263/521 Pages) Hitachi Semiconductor – Hardware Manual

3. Data transfer operations
Transmitting: The procedure for transmitting data is as follows.
(1) Set both SO1 and SCK1 to 1 in PMR2 to designate the SO1 and SCK1 functions.
(2) Clear SNC1 in SCR1 to 0, clear or set SNC0 to 0 or 1, and clear MRKON to 0, to select 8-bit
synchronous mode or 16-bit synchronous mode, and select the serial clock with bits CKS3 to
CKS0. When data is written to SCR1 with MRKON in SCR1 cleared to 0, the internal state of
SCI1 is initialized.
(3) Write the transfer data to SDRL/SDRU.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte to SDRU, lower byte to SDRL
(4) When STF is set to 1 in SCSR1, SCI1 starts operating and transmit data is output from the
SO1.
(5) After transmission is completed, IRRS1 is set to 1 in IRR1.
When an internal clock is used, the serial clock is output from the SCK₁ simultaneously with
transmit data output. When transmission ends, the serial clock is not output until the start flag is
next set to 1. During this interval, the SO₁ continuously outputs the last bit of the previous data.
While transmission is halted, the output value of the SO₁ can be changed by means of the SOL bit
in SCSR1.
Receiving: The procedure for receiving data is as follows.
(1) Set both SI1 and SCK1 to 1 in PMR2 to designate the SI1 and SCK1 functions.
(2) Clear SNC1 in SCR1 to 0, clear or set SNC0 to 0 or 1, and clear MRKON to 0, to select 8-bit
synchronous mode or 16-bit synchronous mode, and select the serial clock with bits CKS3 to
CKS0. When data is written to SCR1 with MRKON in SCR1 cleared to 0, the internal state of
SCI1 is initialized.
(3) When STF is set to 1 in SCSR1, SCI1 starts operating and receive data is taken in from the
SI1.
(4) After reception is completed, IRRS1 is set to 1 in IRR1.
(5) Read the transfer data from SDRL/SDRU.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte from SDRU, lower byte from SDRL
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