HD6433937 Datasheet, PDF (225/521 Pages) Hitachi Semiconductor – Hardware Manual

If an OCRFL write and compare match signal generation occur simultaneously, the
compare match signal is invalid. However, if the written data and the counter value match,
a compare match signal will be generated at that point. As the compare match signal is
output in synchronization with the TCFL clock, a compare match will not result in compare
match signal generation if the clock is stopped.
If a TCFL write and overflow signal output occur simultaneously, the overflow signal is
not output.
3. Clear timer FH, timer FL interrupt request flags (IRRTFH, IRRTFL), timer overflow flags H,
L (OVFH, OVFL) and compare match flags H, L (CMFH, CMFL)
When øw/4 is selected as the internal clock, “Interrupt factor generation signal” will be operated
with øw and the signal will be outputted with øw width. And, “Overflow signal” and “Compare
match signal” are controlled with 2 cycles of øw signals. Those signals are outputted with 2 cycles
width of øw (figure 9-7)
In active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the
term of validity of “Interrupt factor generation signal”, same interrupt request flag is set. (figure 9-
7 1) And, you cannot be cleared timer overflow flag and compare match flag during the term of
validity of “Overflow signal” and “Compare match signal”.
For interrupt request flag is set right after interrupt request is cleared, interrupt process to one time
timer FH, timer FL interrupt might be repeated. (figure 9-7 2) Therefore, to definitely clear
interrupt request flag in active (high-speed, medium-speed) mode, clear should be processed after
the time that calculated with below (1) formula. And, to definitely clear timer overflow flag and
compare match flag, clear should be processed after read timer control status register F (TCSRF)
after the time that calculated with below (1) formula. For ST of (1) formula, please substitute the
longest number of execution states in used instruction. (10 states of RTE instruction when
MULXU, DIVXU instruction is not used, 14 states when MULXU, DIVXU instruction is used) In
subactive mode, there are not limitation for interrupt request flag, timer overflow flag, and
compare match flag clear.
The term of validity of “Interrupt factor generation signal”
= 1 cycle of øw + waiting time for completion of executing instruction
+ interrupt time synchronized with ø = 1/øw + ST × (1/ø) + (2/ø) (second).....(1)
ST: Executing number of execution states
Method 1 is recommended to operate for time efficiency.
Method 1
1. Prohibit interrupt in interrupt handling routine (set IENFH, IENFL to 0).
2. After program process returned normal handling, clear interrupt request flags (IRRTFH,
IRRTFL) after more than that calculated with (1) formula.
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