HD6433937 Datasheet, PDF (402/521 Pages) Hitachi Semiconductor – Hardware Manual

12.6.3 Reset Timing
The following diagram and table describe the timing specifications of the FLEX decoder when it
is reset.
RESET
t_RL
READY
t_RLRH
t_RHRL
Figure 12-15 Reset Timing
Table 12-36 Reset Timing (V_DD = 1.8 V to 3.6 V, T_A = -20ºC to 75ºC)
Characteristic
Conditions
Symbol Min*¹
Max *¹ Unit
RESET Pulse Width
RESET Low to READY High
RESET High to READY Low
t _RL
t _RLRH
t _RHRL
200
–
ns
–
200
ns
76,800 76,800 T*²
Notes: 1. The specifications given in this data sheet indicate the minimum performance level of all
manufacturers of the FLEX decoder. Individual manufacturers may have better
performance than indicated.
2. T is one period of the ø_DEC clock source.
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