HD6433937 Datasheet, PDF (195/521 Pages) Hitachi Semiconductor – Hardware Manual

Bits 7 to 5: Clock output select (TMA7 to TMA5)
Bits 7 to 5 choose which of eight clock signals is output at the TMOW pin. The system clock
divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A ø_w signal divided by
32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode. ø_w is output in all
modes except the reset state.
CWOSR TMA
Bit 7
CWOS TMA7
0
0
1
1
*
Bit 6
TMA6
0
1
0
1
*
Bit 5
TMA5
0
1
0
1
0
1
0
1
*
Clock Output
ø/32
ø/16
ø/8
ø/4
ø_W/32
ø_W/16
ø_W/8
ø_W/4
ø_W
(initial value)
*: Don’t care
Bit 4: Reserved bit
Bit 4 is reserved; it is always read as 1, and cannot be modified.
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