HD6433937 Datasheet, PDF (279/521 Pages) Hitachi Semiconductor – Hardware Manual

7. Serial status register (SSR)
Bit
Initial value
Read/Write
7
TDRE
1
R/(W) ^*
6
RDRF
0
R/(W)^*
5
OER
0
R/(W)^*
4
FER
0
R/(W)^*
3
PER
0
R/(W)^*
2
TEND
1
R
1
MPBR
0
R
0
MPBT
0
R/W
Note: * Only a write of 0 for flag clearing is possible.
SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and
multiprocessor bits.
SSR can be read or written by the CPU at any time, but only a write of 1 is possible to bits TDRE,
RDRF, OER, PER, and FER. In order to clear these bits by writing 0, 1 must first be read.
Bits TEND and MPBR are read-only bits, and cannot be modified.
SSR is initialized to H'84 upon reset, and in standby, module standby, or watch mode.
Bit 7: Transmit data register empty (TDRE)
Bit 7 indicates that transmit data has been transferred from TDR to TSR.
Bit 7
TDRE
0
1
Description
Transmit data written in TDR has not been transferred to TSR
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
Transmit data has not been written to TDR, or transmit data written in
TDR has been transferred to TSR
Setting conditions:
When bit TE in SCR3 is cleared to 0
When data is transferred from TDR to TSR
(initial value)
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