HD6433937 Datasheet, PDF (330/521 Pages) Hitachi Semiconductor – Hardware Manual

11.2 Register Descriptions
11.2.1 A/D Result Registers (ADRRH, ADRRL)
Bit
7654321076543210
ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 —
—
—
—
—
—
Initial value Not Not Not Not Not Not Not Not Not Not — — — — — —
fixed fixed fixed fixed fixed fixed fixed fixed fixed fixed
Read/Write R R R R R R R R R R — — — — — —
ADRRH
ADRRL
ADRRH and ADRRL together comprise a 16-bit read-only register for holding the results of
analog-to-digital conversion. The upper 8 bits of the data are held in ADRRH, and the lower 2
bits in ADRRL.
ADRRH and ADRRL can be read by the CPU at any time, but the ADRRH and ADRRL values
during A/D conversion are not fixed. After A/D conversion is complete, the conversion result is
stored as 10-bit data, and this data is held until the next conversion operation starts.
ADRRH and ADRRL are not cleared on reset.
11.2.2 A/D Mode Register (AMR)
Bit
Initial value
Read/Write
7
6
5
CKS TRGE —
0
0
1
R/W
R/W
—
4
3
2
1
0
—
CH3 CH2 CH1 CH0
1
0
0
0
0
—
R/W R/W R/W R/W
AMR is an 8-bit read/write register for specifying the A/D conversion speed, external trigger
option, and the analog input pins.
Upon reset, AMR is initialized to H'30.
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