HD6433937 Datasheet, PDF (339/521 Pages) Hitachi Semiconductor – Hardware Manual

11.6 Application Notes
• Data in ADRRH and ADRRL should be read only when the A/D start flag (ADSF) in the A/D
start register (ADSR) is cleared to 0.
• Changing the digital input signal at an adjacent pin during A/D conversion may adversely
affect conversion accuracy.
• When A/D conversion is started after clearing module standby mode, wait for 10 ø clock
cycles before starting.
• In active mode and sleep mode, the analog power supply current (AI_STOP1) flows in the ladder
resistance even when the A/D converter is on standby. Therefore, if the A/D converter is not
used, it is recommended that AV_CC be connected to the system power supply and the
ADCKSTP (A/D converter module standby mode control) bit be cleared to 0 in clock stop
register 1 (CKSTPR1).
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