HD6433937 Datasheet, PDF (5/521 Pages) Hitachi Semiconductor – Hardware Manual

Contents
Section 1 Overview............................................................................................................ 1
1.1 Overview ............................................................................................................................ 1
1.2 Internal Block Diagram ...................................................................................................... 5
1.3 Pin Arrangement and Functions......................................................................................... 6
1.3.1 Pin Arrangement ................................................................................................... 6
1.3.2 Pin Functions......................................................................................................... 7
Section 2 CPU ..................................................................................................................... 13
2.1 Overview ............................................................................................................................ 13
2.1.1 Features ................................................................................................................. 13
2.1.2 Address Space....................................................................................................... 14
2.1.3 Register Configuration .......................................................................................... 14
2.2 Register Descriptions ......................................................................................................... 15
2.2.1 General Registers .................................................................................................. 15
2.2.2 Control Registers................................................................................................... 15
2.2.3 Initial Register Values........................................................................................... 16
2.3 Data Formats ...................................................................................................................... 17
2.3.1 Data Formats in General Registers ....................................................................... 18
2.3.2 Memory Data Formats .......................................................................................... 19
2.4 Addressing Modes.............................................................................................................. 20
2.4.1 Addressing Modes................................................................................................. 20
2.4.2 Effective Address Calculation............................................................................... 22
2.5 Instruction Set .................................................................................................................... 26
2.5.1 Data Transfer Instructions..................................................................................... 28
2.5.2 Arithmetic Operations........................................................................................... 30
2.5.3 Logic Operations................................................................................................... 31
2.5.4 Shift Operations .................................................................................................... 31
2.5.5 Bit Manipulations.................................................................................................. 33
2.5.6 Branching Instructions .......................................................................................... 37
2.5.7 System Control Instructions.................................................................................. 39
2.5.8 Block Data Transfer Instruction............................................................................ 40
2.6 Basic Operational Timing .................................................................................................. 42
2.6.1 Access to On-Chip Memory (RAM, ROM) ......................................................... 42
2.6.2 Access to On-Chip Peripheral Modules................................................................ 43
2.7 CPU States ......................................................................................................................... 45
2.7.1 Overview............................................................................................................... 45
2.7.2 Program Execution State....................................................................................... 46
2.7.3 Program Halt State ................................................................................................ 46
2.7.4 Exception-Handling State ..................................................................................... 46
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