HD6433937 Datasheet, PDF (223/521 Pages) Hitachi Semiconductor – Hardware Manual

4. TCF clear timing
TCF can be cleared by a compare match with OCRF.
5. Timer overflow flag (OVF) set timing
OVF is set to 1 when TCF overflows from H'FFFF to H'0000.
6. Compare match flag set timing
The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match.
The compare match signal is generated in the last state during which the values match (when TCF
is updated from the matching value to a new value). When TCF matches OCRF, the compare
match signal is not generated until the next counter clock.
7. Timer F operation modes
Timer F operation modes are shown in table 9-10.
Table 9-10 Timer F Operation Modes
Operation
Mode
Reset Active Sleep
Watch
Module
Subactive Subsleep Standby Standby
TCF
Reset Functions Functions Functions/ Functions/ Functions/ Halted
Halted
Halted* Halted* Halted*
OCRF
Reset Functions Held
Held
Functions Held
Held
Held
TCRF
Reset Functions Held
Held
Functions Held
Held
Held
TCSRF
Note: *
Reset Functions Held
Held
Functions Held
Held
Held
When ø_w/4 is selected as the TCF internal clock in active mode or sleep mode, since
the system clock and internal clock are mutually asynchronous, synchronization is
maintained by a synchronization circuit. This results in a maximum count cycle error of
1/ø (s). When the counter is operated in subactive mode, watch mode, or subsleep
mode, ø_w/4 must be selected as the internal clock. The counter will not operate if any
other internal clock is selected.
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