HD6433937 Datasheet, PDF (429/521 Pages) Hitachi Semiconductor – Hardware Manual

A.3 Number of Execution States
The tables here can be used to calculate the number of states required for instruction execution.
Table A-4 indicates the number of states required for each cycle (instruction fetch, read/write,
etc.), and table A-3 indicates the number of cycles of each type occurring in each instruction. The
total number of states required for execution of an instruction can be calculated from these two
tables as follows:
Execution states = I × S_I + J × S_J + K × S_K + L × S_L+ M × S_M + N × S_N
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A-4:
I = L = 2, J = K = M = N= 0
From table A-3:
S_I = 2, S_L = 2
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A-4:
I = 2, J = K = 1, L = M = N = 0
From table A-3:
S_I = S_J = S_K = 2
Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8
Table A-3 Number of Cycles in Each Instruction
Execution Status
Access Location
(instruction cycle)
On-Chip Memory
On-Chip Peripheral Module
Instruction fetch
S_I
2
—
Branch address read
S_J
Stack operation
S_K
Byte data access
S_L
2 or 3*
Word data access
S_M
—
Internal operation
S_N
1
1
Note: * Depends on which on-chip module is accessed. See 2.9.1, Notes on Data Access for
details.
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