HD6433937 Datasheet, PDF (354/521 Pages) Hitachi Semiconductor – Hardware Manual

OFD₁ OFD₀
0
0
0
1
1
0
1
1
Frequency Difference
+/- 300 ppm
+/- 150 ppm
+/- 75 ppm
+/- 0 ppm
PCE: Partial Correlation Enable. When this bit is set, partial correlation of addresses is enabled.
When partial correlation is enabled, the FLEX decoder will shutdown the receiver before the end
of the last FLEX block which contains addresses if it can determine that none of the addresses in
that FLEX block will match any enabled address in the FLEX decoder. When this bit is cleared,
the receiver will be controlled as it was in previous versions of the FLEX decoder. (value after
reset=0)
SP: Signal Polarity. These bits set the polarity of EXTS1 and EXTS0 input signals. (value after
reset=0) The polarity of the EXTS0 and EXTS1 bits will be determined by the receiver design.
SP₁ SP₀
00
01
10
11
Signal Polarity
EXTS1
Normal
Normal
Inverted
Inverted
EXTS0
Normal
Inverted
Normal
Inverted
FSK Modulation
@ SP = 0,0
+ 4800 Hz
+1600 Hz
- 1600 Hz
- 4800 Hz
EXTS1
1
1
0
0
EXTS0
0
1
1
0
SME: Synchronous Mode Enable. When this bit is set, a Status Packet will be automatically sent
whenever the SMU (synchronous mode update) bit in the Status Packet is set. The host can use the
SM (synchronous mode) bit in the Status Packet as an in-range/out-of-range indication. (value
after reset=0)
MOT: Maximum Off Time. This bit has no effect if AST in the Timing Control Packet is non-
zero. When AST=0 and MOT=0, asynchronous A-word searches will time-out in 4 minutes. When
AST=0 and MOT=1, asynchronous A-word searches will time-out in 1 minute. (value after
reset=0)
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