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HD6433937 Datasheet, PDF (94/521 Pages) Hitachi Semiconductor – Hardware Manual
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Table 3-5 Conditions under which Interrupt Request Flag is Set to 1
Interrupt Request
Flags Set to 1
IRR1 IRRI4
IRRI3
IRRI2
IRRI1
IRRI0
IWPR
IWPF7
IWPF6
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
Conditions
When PMR1 bit IRQ4 is changed from 0 to 1 while pin IRQ4 is low and IEGR
bit IEG4 = 0.
When PMR1 bit IRQ4 is changed from 1 to 0 while pin IRQ4 is low and IEGR
bit IEG4 = 1.
When PMR1 bit IRQ3 is changed from 0 to 1 while pin IRQ3 is low and IEGR
bit IEG3 = 0.
When PMR1 bit IRQ3 is changed from 1 to 0 while pin IRQ3 is low and IEGR
bit IEG3 = 1.
When PMR1 bit IRQ2 is changed from 0 to 1 while pin IRQ2 is low and IEGR
bit IEG2 = 0.
When PMR1 bit IRQ2 is changed from 1 to 0 while pin IRQ2 is low and IEGR
bit IEG2 = 1.
When PMR1 bit IRQ1 is changed from 0 to 1 while pin IRQ1 is low and IEGR
bit IEG1 = 0.
When PMR1 bit IRQ1 is changed from 1 to 0 while pin IRQ1 is low and IEGR
bit IEG1 = 1.
When PMR3 bit IRQ0 is changed from 0 to 1 while IRQ0 is low and IEGR bit
IEG0 = 0.
When PMR3 bit IRQ0 is changed from 1 to 0 while IRQ0 is low and IEGR bit
IEG0 = 1.
When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP7 is low.
When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP6 is low.
When PMR5 bit WKP5 is changed from 0 to 1 while pin WKP5 is low.
When PMR5 bit WKP4 is changed from 0 to 1 while pin WKP4 is low.
When PMR5 bit WKP3 is changed from 0 to 1 while pin WKP3 is low.
When PMR5 bit WKP2 is changed from 0 to 1 while pin WKP2 is low.
When PMR5 bit WKP1 is changed from 0 to 1 while pin WKP1 is low.
When PMR5 bit WKP0 is changed from 0 to 1 while pin WKP0 is low.
Figure 3-7 shows the procedure for setting a bit in a port mode register and clearing the interrupt
request flag.
When switching a pin function, mask the interrupt before setting the bit in the port mode register.
After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the
interrupt request flag from 1 to 0. If the instruction to clear the flag is executed immediately after
the port mode register access without executing an intervening instruction, the flag will not be
cleared.
An alternative method is to avoid the setting of interrupt request flags when pin functions are
switched by keeping the pins at the high level so that the conditions in table 3-5 do not occur.
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