HD6433937 Datasheet, PDF (377/521 Pages) Hitachi Semiconductor – Hardware Manual

4. Short Instruction Vector
Table 12-24 Short Instruction Vector Packet Bit Assignments
Byte 3
Byte 2
Byte 1
Byte 0
Bit 7
0
e
x
d₄
Bit 6
WN ₆
p₁
x
d₃
Bit 5
WN₅
p₀
d ₁₀
d₂
Bit 4
WN₄
x
d₉
d₁
Bit 3
WN₃
x
d₈
d₀
Bit 2
WN ₂
V₂
d₇
i₂
Bit 1
WN₁
V₁
d₆
i₁
Bit 0
WN ₀
V₀
d₅
i₀
V: 001 for a Short Instruction Vector
WN: Word number of vector (2 - 87 decimal). Describes the location of the vector word in the
frame.
e: Set if more than 2 bit errors are detected in the word or, if after error correction, the check
character calculation fails.
p: Phase on which the vector was found (0=a, 1=b, 2=c, 3=d)
d: Data bits whose definition depend on the i bits in this packet according to the following table.
Note that if this vector is received on a long address and the e bit in this packet is not set, the
decoder will send a Message Packet immediately following the Vector Packet. All message bits in
the message packet are unused and should be ignored for all modes except the Temporary address
assignment with MSN (i₂ i₁ i₀ =010).
i₂ i₁ I₀ d₁₀ d₉ d₈ d₇ d₆ d₅ d₄ d₃ d₂ d₁ d₀ Description
0 0 0 a₃ a₂ a₁ a₀ f₆ f₅ f₄ f₃ f₂ f₁ f₀ Temporary address assignment*¹
0 0 1 d₁₀ d₉ d₈ d₇ d₆ d₅ d₄ d₃ d₂ d₁ d₀ 11 Event Flags for System Event
0 1 0 a₃ a₂ a₁ a₀ f₆ N₅ N₄ N₃ N₂ N₁ N₀ Temporary address assignment with MSN*²
011
Reserved
100
Reserved
101
Reserved
110
Reserved
111
Reserved for test
Notes: 1. Assigned temporary address (a) and assigned frame (f). See 12.5.4, Operation of a
Temporary Address for a description of the use of these fields.
2. Assigned temporary address (a), MSb of assigned frame (f₆ ), and message sequence
number (N). The message packet sent with this instruction on long addresses contains
extra frame information, see 12.5.4, Operation of a Temporary Address for a description
and for details on the use of the other fields.
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