HD6433937 Datasheet, PDF (83/521 Pages) Hitachi Semiconductor – Hardware Manual

Bit 1: Timer C interrupt request flag (IRRTC)
Bit 1
IRRTC
0
1
Description
Clearing conditions:
When IRRTC= 1, it is cleared by writing 0
(initial value)
Setting conditions:
When the timer C counter value overflows (from H'FF to H'00) or underflows
(from H'00 to H'FF)
Bit 0: Reserved bit
Bit 0 is reserved: it is always read as 0 and cannot be modified.
6. Wakeup Interrupt Request Register (IWPR)
Bit
7
6
5
4
Initial value
Read/Write
IWPF7
0
R/(W)*
IWPF6
0
R/(W)*
IWPF5
0
R/(W)*
IWPF4
0
R/(W)*
3
IWPF3
0
R/(W)*
2
IWPF2
0
R/(W)*
1
IWPF1
0
R/(W)*
0
IWPF0
0
R/(W)*
Note: * All bits can only be written with 0, for flag clearing.
IWPR is an 8-bit read/write register containing wakeup interrupt request flags. When one of pins
WKP₇ to WKP₀ is designated for wakeup input and a rising or falling edge is input at that pin, the
corresponding flag in IWPR is set to 1. A flag is not cleared automatically when the
corresponding interrupt is accepted. Flags must be cleared by writing 0.
Bits 7 to 0: Wakeup interrupt request flags (IWPF7 to IWPF0)
Bit n
IWPFn
0
1
Description
Clearing conditions:
When IWPFn= 1, it is cleared by writing 0
(initial value)
Setting conditions:
When pin WKP_n is designated for wakeup input and a rising or falling edge is input at
that pin
(n = 7 to 0)
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