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HD6433937 Datasheet, PDF (485/521 Pages) Hitachi Semiconductor – Hardware Manual | |||
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IRR1âInterrupt request register 1
Bit
7
6
5
IRRTA IRRS1 â
Initial value
0
0
1
Read/Write R/(W)* R/(W)* â
H'F6
System control
4
IRRI4
0
R/(W)*
3
IRRI3
0
R/(W)*
2
IRRI2
0
R/(W)*
1
IRRI1
0
R/(W)*
0
IRRI0
0
R/(W)*
IRQ4 to IRQ0 interrupt request flags
0 Clearing conditions:
When IRRIn = 1, it is cleared by writing 0
1 Setting conditions:
When pin IRQn is designated for interrupt
input and the designated signal edge is input
(n = 4 to 0)
Note: IRQ0 is an internal signal that performs interfacing
to the FLEX⢠decoder incorporated in the chip.
SCI1 interrupt request flag
0 Clearing conditions:
When IRRS1 = 1, it is cleared by writing 0
1 Setting conditions:
When SCI1 completes transfer
Note: SCI1 is an internal function that performs
interfacing to the FLEX⢠decoder incorporated
in the chip.
Timer A interrupt request flag
0 Clearing conditions:
When IRRTA = 1, it is cleared by writing 0
1 Setting conditions:
When the timer A counter value overflows (rom H'FF to H'00)
Note: * Bits 7, 6, and 4 to 0 can only be written with 0, for flag clearing.
473
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