HD6433937 Datasheet, PDF (239/521 Pages) Hitachi Semiconductor – Hardware Manual

6. Timer G operation modes
Timer G operation modes are shown in table 9-13.
Table 9-13 Timer G Operation Modes
Operation Mode
Reset Active
Sleep
Watch
Module
Subactive Subsleep Standby Standby
TCG Input capture Reset Functions* Functions* Functions/ Functions/ Functions/ Halted Halted
halted* halted* halted*
Interval
Reset Functions* Functions* Functions/ Functions/ Functions/ Halted Halted
halted* halted* halted*
ICRGF
Reset Functions* Functions* Functions/ Functions/ Functions/ Held
halted* halted* halted*
Held
ICRGR
Reset Functions* Functions* Functions/ Functions/ Functions/ Held
halted* halted* halted*
Held
TMG
Note:
Reset Functions Held
Held
Functions Held
Held Held
* When øw/4 is selected as the TCG internal clock in active mode or sleep mode, since
the system clock and internal clock are mutually asynchronous, synchronization is
maintained by a synchronization circuit. This results in a maximum count cycle error of
1/ø(s). When øw/4 is selected as the TCG internal clock in watch mode, TCG and the
noise canceler operate on the øw/4 internal clock without regard to the ø subclock
(øw/8, øw/4, øw/2). Note that when another internal clock is selected, TCG and the
noise canceler do not operate, and input of the input capture input signal does not result
in input capture.
To operate the timer G in subactive mode or subsleep mode, select øw/4 as the TCG
internal clock and øw/2 as the subclock ø_SUB. Note that when other internal clock is
selected, or when øw/8 or øw/4 is selected as the subclock ø_SUB, TCG and the noise
canceler do not operate.
9.5.5 Application Notes
1. Internal clock switching and TCG operation
Depending on the timing, TCG may be incremented by a switch between difference internal clock
sources. Table 9-14 shows the relation between internal clock switchover timing (by write to bits
CKS1 and CKS0) and TCG operation.
When TCG is internally clocked, an increment pulse is generated on detection of the falling edge
of an internal clock signal, which is divided from the system clock (ø) or subclock (øw). For this
reason, in a case like No. 3 in table 9-14 where the switch is from a high clock signal to a low
clock signal, the switchover is seen as a falling edge, causing TCG to increment.
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