HD6433937 Datasheet, PDF (345/521 Pages) Hitachi Semiconductor – Hardware Manual

12.2 SPI Packets
All data communicated between the FLEX decoder and the host MCU is transmitted on the SPI in
32-bit packets. Each packet consists of an 8-bit ID followed by 24 bits of information. The FLEX
decoder uses the SPI bus in full duplex mode. In other words, whenever a packet communication
occurs, the data in both directions is valid packet data.
The SPI interface consists of a READY pin and four SPI pins (SS, SCK, MOSI, and MISO).The
SS is used as a chip select for the FLEX decoder. The SCK is a clock supplied by the host MCU.
The data from the host is transmitted on the MOSI line. The data from the FLEX decoder is
transmitted on the MISO line.
Timing requirements for SPI communication are specified in 12.6.1, SPI Timing.
12.2.1 Packet Communication Initiated by the Host
Refer to figure 12-4. When the host sends a packet to the FLEX decoder, it performs the following
steps:
1. Select the FLEX decoder by driving the SS pin low.
2. Wait for the FLEX decoder to drive the READY pin low.
3. Send the 32-bit packet.
4. De-select the FLEX decoder by driving the SS pin high.
5. Repeat steps 1 through 4 for each additional packet.
SS
1
4
READY
2
SCK
MOSI
MISO
3
D31 D1 D0
D31 D1 D0
D31 D1 D0
D31 D1 D0
D31 D1 D0
D31 D1 D0
High impedance state
Figure 12-4 Typical Multiple Packet Communications Initiated by the Host
When the host sends a packet, it will also receive a valid packet from the FLEX decoder. If the
FLEX decoder is enabled (see 12.3.1, Checksum Packet for a definition of enabled) and has no
other packets waiting to be sent, the FLEX decoder will send a status packet.
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