HD6433937 Datasheet, PDF (85/521 Pages) Hitachi Semiconductor – Hardware Manual

When these pins are designated as pins IRQ₄ to IRQ₁ in port mode register 3 and 1 and the
designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt.
Recognition of these interrupt requests can be disabled individually by clearing bits IEN4 to IEN1
to 0 in IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR.
When IRQ₄ to IRQ₁ interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
numbers 8 to 5 are assigned to interrupts IRQ₄ to IRQ₁. The order of priority is from IRQ₁ (high)
to IRQ₄ (low). Table 3-2 gives details.
3.3.4 Internal Interrupts
1. Internal interrupts
There are 23 internal interrupts that can be requested by the on-chip peripheral modules. When a
peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1.
Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in
IENR1 or IENR2. All these interrupts can be masked by setting the I bit to 1 in CCR. When
internal interrupt handling is initiated, the I bit is set to 1 in CCR. Vector numbers from 20 to 13,
11, and 10 are assigned to these interrupts. Table 3-2 shows the order of priority of interrupts from
on-chip peripheral modules.
2. IRQ₀ interrupt
The IRQ₀ interrupt is requested by the READY input signal from the FLEX™ decoder
incorporated in the chip. Rising or falling edge sensing can be selected for the IRQ₀ interrupt by
means of bit IEG0 in IEGR. When the designated edge is input while the IRQ₀ function is
selected by bit IRQ₀ in PMR3, bit IRRI0 is set to 1 in IRR1, and an interrupt is requested.
Interrupt request recognition can be disabled by clearing bit IEN0 to 0 in IENR1. In addition, all
interrupts can be masked by setting the I bit to 1 in CCR. When IRQ₀ interrupt exception handling
is initiated, the I bit is set to 1 in CCR. The vector number for IRQ₀ interrupt exception handling
is 4. See table 3-2 for details.
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