HD6433937 Datasheet, PDF (457/521 Pages) Hitachi Semiconductor – Hardware Manual

TCSRW—Timer control/status register W
H'B2 Watchdog timer
Bit
Initial value
Read/Write
7
B6WI
1
R
6
TCWE
0
R/(W)^*
5
B4WI
1
R
4
TCSRWE
0
R/(W)^*
3
B2WI
1
R
2
WDON
0
R/(W)^*
1
B0WI
1
R
0
WRST
0
R/(W) ^*
Watchdog timer reset
0 [Clearing conditions]
• Reset by RES pin
• When TCSRWE = 1, and 0 is written in both B0WI and WRST
1 [Setting condition]
When TCW overflows and a reset signal is generated
Bit 0 write inhibit
0 Bit 0 is write-enabled
1 Bit 0 is write-protected
Watchdog timer on
0 Watchdog timer operation is disabled
1 Watchdog timer operation is enabled
Bit 2 write inhibit
0 Bit 2 is write-enabled
1 Bit 2 is write-protected
Timer control/status register W write enable
0 Data cannot be written to bits 2 and 0
1 Data can be written to bits 2 and 0
Bit 4 write inhibit
0 Bit 4 is write-enabled
1 Bit 4 is write-protected
Timer counter W write enable
0 Data cannot be written to TCW
1 Data can be written to TCW
Bit 6 write inhibit
0 Bit 6 is write-enabled
1 Bit 6 is write-protected
Note: * Write is permitted only under certain conditions.
445