HD6433937 Datasheet, PDF (258/521 Pages) Hitachi Semiconductor – Hardware Manual

Bit 3: Clock source select 3 (CKS3)
Bit 3 selects the clock source to be supplied and sets the SCK₁ to input or output mode.
Bit 3
CKS3
Description
0
Clock source is prescaler S, SCK₁ is output
(initial value)
1
Clock source is external clock, SCK₁ is input*
Note: * SCI1 is an internal function that performs interfacing to the on-chip FLEX™ decoder. It
cannot be used with SCK1 input selected.
Bits 2 to 0: Clock select 2 to 0 (CKS2 to CKS0)
When CKS3 is cleared to 0, bits 2 to 0 selects the prescaler division ratio and the serial clock
cycle.
Bit 2
CKS2
0
0
0
0
1
1
1
1
Bit 1
CKS1
0
0
1
1
0
0
1
1
Bit 0
CKS0
0
1
0
1
0
1
0
1
Prescaler Division Ratio
ø/1024 (initial value)
ø/256
ø/64
ø/32
ø/16
ø/8
ø/4
ø_W/4
Serial Clock Cycle
ø = 2.5 MHz
409.6 µs
102.4 µs
25.6 µs
12.8 µs
6.4 µs
3.2 µs
1.6 µs
50 µs or 104.2 µs
2. Serial control status register 1 (SCSR1)
Bit
7
6
5
4
3
—
SOL ORER —
—
Initial value
1
0
0
1
1
Read/Write
—
R/W R/(W)* —
—
Note: * Only a write of 0 for flag clearing is possible.
2
1
0
—
MTRF STF
1
0
0
—
R
R/W
SCSR1 is an 8-bit register that indicates the operational and error status of SCI1.
Upon reset, SCSR1 is initialized to H'9C.
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