HD6433937 Datasheet, PDF (231/521 Pages) Hitachi Semiconductor – Hardware Manual

4. Timer mode register G (TMG)
Bit:
7
6
5
4
3
OVFH
OVFL
OVIE
IIEGS CCLR1
Initial value: 0
0
0
0
0
Read/Write: R/(W)^* R/(W)^* R/W
R/W
R/W
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
2
CCLR0
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
TMG is an 8-bit read/write register that performs TCG clock selection from four internal clock
sources, counter clear selection, and edge selection for the input capture input signal interrupt
request, controls enabling of overflow interrupt requests, and also contains the overflow flags.
TMG is initialized to H'00 upon reset.
Bit 7: Timer overflow flag H (OVFH)
Bit 7 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture
input signal is high. This flag is set by hardware and cleared by software. It cannot be set by
software.
Bit 7
OVFH
0
1
Description
Clearing conditions:
After reading OVFH = 1, cleared by writing 0 to OVFH
Setting conditions:
Set when TCG overflows from H'FF to H'00
(initial value)
Bit 6: Timer overflow flag L (OVFL)
Bit 6 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture
input signal is low, or in interval operation. This flag is set by hardware and cleared by software.
It cannot be set by software.
Bit 6
OVFL
0
1
Description
Clearing conditions:
After reading OVFL = 1, cleared by writing 0 to OVFL
Setting conditions:
Set when TCG overflows from H'FF to H'00
(initial value)
219