HD6433937 Datasheet, PDF (199/521 Pages) Hitachi Semiconductor – Hardware Manual

2. Time base operation
When bit TMA3 in TMA is set to 1, timer A functions as a time base by counting clock signals
output by prescaler W. The overflow period of timer A is set by bits TMA1 and TMA0 in TMA.
A choice of four periods is available. In time base operation (TMA3 = 1), setting bit TMA2 to 1
clears both TCA and prescaler W to their initial values of H'00.
3. Clock output
Setting bit TMOW in port mode register 1 (PMR1) to 1 causes a clock signal to be output at pin
TMOW. Nine different clock output signals can be selected by means of bits TMA7 to TMA5 in
TMA and bit CWOS in CWOSR. The system clock divided by 32, 16, 8, or 4 can be output in
active mode and sleep mode. A ø_w signal divided by 32, 16, 8, or 4 can be output in active mode,
sleep mode, watch mode, subactive mode, and subsleep mode. The ø_w clock is output in all modes
except the reset state.
9.2.4 Timer A Operation States
Table 9-4 summarizes the timer A operation states.
Table 9-4 Timer A Operation States
Operation Mode
Reset Active Sleep
Watch
Sub-
active
Sub-
sleep
Module
Standby Standby
TCA Interval
Reset Functions Functions Halted Halted Halted Halted Halted
Time base
Reset Functions Functions Functions Functions Functions Halted Halted
TMA
Reset Functions Retained Retained Functions Retained Retained Retained
Note:
When the time base function is selected as the internal clock of TCA in active mode or
sleep mode, the internal clock is not synchronous with the system clock, so it is
synchronized by a synchronizing circuit. This may result in a maximum error of 1/ø (s) in the
count cycle.
9.2.5 Application Note
When bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) is cleared to 0, bit 3 (TMA3) of
the timer mode register A (TMA) cannot be rewritten.
Set bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) to 1 before rewriting bit 3 (TMA3)
of the timer mode register A (TMA).
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