HD6433937 Datasheet, PDF (198/521 Pages) Hitachi Semiconductor – Hardware Manual

4. Subclock Output Select Register (CWOSR)
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
CWOS
Initial value: 1
1
1
1
1
1
1
0
Read/Write: —
—
—
—
—
—
—
R/W
CWOSR is an 8-bit read/write register that selects the clock to be output from the TMOW pin.
CWOSR is initialized to H'FE by a reset.
Bits 7 to 1: Reserved bits
Bits 7 to 1 are reserved; they are always read as 1 and cannot be modified.
Bit 0: TMOW pin clock select (CWOS)
Bit 0 selects the clock to be output from the TMOW pin.
Bit 0
CWOS
0
1
Description
Clock output from timer A is output (see TMA)
ø_W is output
(initial value)
9.2.3 Timer Operation
1. Interval timer operation
When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit
interval timer.
Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval
timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in
TMA; any of eight internal clock signals output by prescaler S can be selected.
After the count value in TCA reaches H'FF, the next clock signal input causes timer A to
overflow, setting bit IRRTA to 1 in interrupt request register 1 (IRR1). If IENTA = 1 in interrupt
enable register 1 (IENR1), a CPU interrupt is requested.*
At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as
an interval timer that generates an overflow output at intervals of 256 input clock pulses.
Note: * For details on interrupts, see 3.3, Interrupts.
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